The present invention relates to a semiconductor device. More particularly, the invention relates to the structure of a laterally diffused MOS (metal oxide semiconductor) transistor having a separation insulating film between the gate and the drain.
For element isolation in advanced logic MOS transistors, the STI (shallow trench isolation) structure is often used in place of the LOCOS (local oxidation of silicon) structure so as to reduce the isolation area. Where a high breakdown voltage LDMOS (laterally diffused MOS) transistor is to be formed, the STI structure is known to be used for internal gate-drain isolation in order to ensure breakdown voltage.
Patent Literature 1 (Japanese Unexamined Patent Application Publication No. 2010-258226) states that in the N-channel type LDMOS transistor, the edge of the STI structure is staggered to prevent the fluctuation of on-resistance caused by the concentration of electric fields at the source-side edge of the STI structure.
Patent Literature 2 (U.S. Pat. No. 8,357,986) states that in the LDMOS transistor, the gate electrode is partially embedded in a trench formed over the principal plane of the semiconductor substrate. In this case, the gate electrode is not formed on the drain region side away from the trench so as to reduce the capacitance between the gate electrode and the drain region. Also, for purpose of capacitance reduction, the n type drift region is not formed on the source region side away from the trench. The insulating film isolating the gate electrode in the trench from the substrate making up the side walls and bottom of the trench is approximately as thick as the gate insulating film of the LDMOS transistor because the inside of the substrate in contact with the insulating film serves as the channel region.
Non-Patent Literature 1 states that in the substrate of the P-channel type LDMOS transistor, an electric field is oriented in a direction in which electrons would be injected into the gate oxide film, so that when the electric field is concentrated over the edge of the STI structure, electrons are accelerated and injected into the gate oxide film. It is also stated that the damage caused by the electron injection destroys the gate oxide film at the upper edge of the STI structure.    (Non-Patent Literature 1: Investigation of Multistage Linear Region Drain Current Degradation and Gate-Oxide Breakdown Under Hot-Carrier Stress in BCD HV PMOS, Yu-Hui Huang et al., Proc. of IRPS'11, pp. 444-448)
Non-Patent Literature 2 states that in addition to the above-cited breakdown of the gate oxide film, breakdown voltage drops due to an unbalanced electric field.    (Non-Patent Literature 2: HCI-induced off-state I-V curve shifting and subsequent destruction in an STI-based LD-PMOS transistor, H. Fujii et al., Proc. of ISPSD'13, pp. 379-382)